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Register renaming
Results: 28

#	Item
11	Today’s Big Idea CS252 Graduate Computer Architecture Lecture 18: Add to Reading List Source URL: www.cs.berkeley.edu Language: English - Date: 2003-06-11 14:31:51 Central processing unit Branch predictor Instruction set architectures Alpha 21264 Register renaming DEC Alpha CPU cache Out-of-order execution Re-order buffer Computer architecture Computer hardware Computer engineering
12	Computer Science 252: Graduate Computer Architecture University of California Dept. of Electrical Engineering and Computer Sciences David E. Culler TA: Steve Sorkin Take Home due 5/20 Spring 2003 Add to Reading List Source URL: www.cs.berkeley.edu Language: English - Date: 2003-06-11 14:32:04 Central processing unit CPU cache Cache Computer memory Parallel computing Processor register Register renaming Cell Computer architecture Computing Computer hardware
13	Lecture 5: VLIW, Software Pipelining, and Limits to ILP Professor David A. Patterson Computer Science 252 Spring 1998 Add to Reading List Source URL: www.cs.berkeley.edu Language: English - Date: 1998-02-06 15:14:03 Computer engineering Register renaming Branch misprediction Prediction R10000 Loop unwinding Branch Lookup table DEC Alpha Computing Computer architecture Branch predictor
14	Lecture 4: Tomasulo Algorithm and Dynamic Branch Prediction Professor David A. Patterson Computer Science 252 Spring 1998 Add to Reading List Source URL: www.cs.berkeley.edu Language: English - Date: 1998-02-04 19:47:26 Instruction set Computing Computer science Electronics Algorithms Tomasulo algorithm Register renaming
15	IEEE TRANSACTIONS ON DEPENDABLE AND SECURE COMPUTING (TDSC) 1 Using Register Lifetime Predictions to Protect Register Files Against Soft Errors Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2008-08-29 19:16:16 Central processing unit Computer memory Register renaming CPU cache Register file Branch predictor Parity bit Processor register 64-bit Computer architecture Computer hardware Computing
16	Using Register Lifetime Predictions to Protect Register Files Against Soft Errors∗ Pablo Montesinos, Wei Liu and Josep Torrellas Department of Computer Science University of Illinois at Urbana-Champaign {pmontesi, liuw Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2007-04-07 18:15:20 Central processing unit Computer memory Register renaming Register file CPU cache Branch predictor Parity bit 64-bit Processor register Computer hardware Computer architecture Computing
17	Shield: Cost-Effective Soft-Error Protection for Register Files Pablo Montesinos, Wei Liu, and Josep Torrellas University of Illinois at Urbana-Champaign {pmontesi, liuwei, torrellas}@cs.uiuc.edu http://iacoma.cs.uiuc.ed Add to Reading List Source URL: iacoma.cs.uiuc.edu Language: English - Date: 2006-10-02 23:53:51 Central processing unit Computer memory Register renaming Register file CPU cache Branch predictor Processor register Parity bit Computer hardware Computer architecture Computing
18	Speculative Updates of Local and Global Branch History: A Quantitative Analysis Kevin Skadron SKADRON @ CS . VIRGINIA . EDU Add to Reading List Source URL: www.jilp.org Language: English - Date: 2003-06-05 15:33:55 Central processing unit Instruction set architectures Branch predictor Alpha 21264 CPU cache Out-of-order execution Register renaming Microarchitecture DEC Alpha Computer architecture Computer engineering Computer hardware
19	--06 April 20, 2000 Cheap Out-of-Order Execution using Delayed Issue J.P. Grossman Add to Reading List Source URL: www.ai.mit.edu Language: English - Date: 2001-05-16 17:41:22 Parallel computing Central processing unit Classes of computers Register renaming Superscalar Very long instruction word Software pipelining Tomasulo algorithm Instruction set Computer architecture Computing Computer engineering
20	Understanding POWER Multiprocessors Susmit Sarkar1 1 Peter Sewell1 Add to Reading List Source URL: www.cl.cam.ac.uk Language: English - Date: 2011-10-26 17:19:12 Computer memory Central processing unit Parallel computing Threads Memory barrier Memory model Data dependency Register renaming Microarchitecture Computing Computer architecture Concurrent computing